I. Field of the Invention
The present invention relates generally to memory devices and particularly to flash memory devices.
II. Description of the Related Art
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include portable computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code, system data such as a basic input/output system (BIOS), and other firmware can typically be stored in flash memory devices.
A synchronous flash memory device is a flash memory device that has a synchronous dynamic random access memory (SDRAM) interface. This enables the synchronous flash device to operate at much higher speeds than a typical flash memory.
An erase operation in flash memory is typically comprised of three separate activities. The entire array is pre-programmed, the memory block is erased, and a Vt tightening operation is performed.
The array is pre-programmed in order to reduce the chances of the cells going into a depletion mode. As the cells in a flash memory device get erased, they may get erased to the point where they go into depletion and conduct current even when those cells have a gate voltage of 0 V. This affects the reading of all other cells in their respective columns. By pre-programming the memory, the cells start from a known programmed state and are therefore less likely to go into depletion.
The erase operation is then conducted to ensure that all cells are erased to at least a minimum level. At the end of the erase operation, there is no guarantee that some cells have not been over-erased. In this case, a Vt tightening operation is performed.
The Vt tightening operation is a short programming pulse that is intended to pull memory cells that are depleted back into the normal population of erased cells. Vt is the gate voltage to which the memory cell is programmed. This operation may be accomplished by pulsing the cell, then checking for the erased state. This operation is repeated until all depleted cells are left with proper threshold voltages.
Most flash memory devices are read in a byte or word mode. In this case, the interaction between bit lines (also referred to in the art as columns or data lines) is not an issue since only 8 or 16 out of 2000 or 4000 columns, for example, are being sensed at any one time. However, in synchronous flash memory devices, 8000 bit lines may be sensed at a time. This makes the interaction between adjacent bit lines an important part of the read operation.
If an adjacent bit line is defective or over-erased, it pulls down at a faster rate than a normal bit line. The coupling capacitance between the two bit lines shows up as an AC injected current in the adjacent bit line. This current is going to make the cells in that adjacent bit line appear as erased when they may actually be programmed.
In a synchronous flash device, the defective bit lines do not get preprogrammed and are therefore continually erased until they go into an over-erasure condition. These bit lines then discharge even more quickly thus causing greater problems with adjacent bit lines.
An additional problem is that typical preprogram operations may try to verify the preprogrammed data up to one thousand times. This increases the test time and the time it takes to do any erase operation. There is a resulting need in the art for a way to reduce or eliminate the effect that defective or over-erased bit lines have on adjacent bit lines while also reducing the time required to perform a preprogram operation.